二进制转译加速方法及其在低电压处理器中的应用研究

发布时间：2019-06-15 11:15

【摘要】：随着移动互联网和物联网的发展,基于ARM的嵌入式处理器越来越普及,例如智能手机和智能平板等。一方面,代码的二进制兼容性已经成为新的处理器架构能否进入嵌入式市场的主要阻碍。另一方面,这些处理器往往采用电池供电,面临严重的功耗问题。动态二进制转译技术不但能够有效解决上述代码兼容性问题,实现跨平台执行；还能够实时获得程序的运行信息,有针对性的对程序进行动态优化,以获得最佳能效。本文围绕动态二进制转译的关键技术进行了研究,提出了面向动态转译的加速方法；并利用二进制转译的跨平台特性和动态优化特性,将二进制转译技术和瞬态错误自适应的低电压处理器设计技术相结合,以有效提高处理器能效。本文主要研究内容和创新点为：1、基于转移指令特性的动态转译方法。针对传统方法统一转译转移指令导致转译器效率较低,基于转移目标地址在函数内外的不同特征提出直接映射和指令类型转译策略组合的动态转译方法。对函数内转移指令,直接采用目标架构中对应的分支指令进行映射,通过转移前后指令转译码无缝链接高效转译条件分支指令,且无需生成源寄存器到内存同步指令；对函数间转移指令,区别对待函数转移和其他转移指令,通过将源程序函数转移指令属性继承给转译码以提高目标机转移预测器准确率。2、基于高速缓存负荷均衡的动态转译方法。针对动态转译时指令和数据高速缓存访问负荷大幅增加且增幅不均衡导致的转译器性能下降问题,提出基于指令与数据高速缓存访问负荷动态均衡的软硬件协同转译方法。该方法为处理器设计高速缓存负荷平衡状态,该状态将数据高速缓存分为普通区和负荷平衡区,普通区缓存正常的程序数据,负荷平衡区通过负荷转化通道吸收动态转译器调度器将源机器代码空间地址向目标机器代码空间地址转换时在指令高速缓存上产生的部分负荷,提高数据高速缓存利用率。3、基于瞬态错误预测模型的单周期纠错的低电压处理器。基于低电压处理器中的瞬态错误在流水线中分布的局部性和可预测性,提出软硬件协同设计的单周期纠错的低电压处理器设计方法。该方法的核心思想是基于动态转译技术建立处理器瞬态错误预测模型。该模型在程序编译时对可能出错的指令流进行预测。对于那些可能出错的指令流,通过处理器瞬态错误消除编程接口,在编译时即将可能出现的瞬态错误规避掉,有效提高系统的容错能力和能效。4、基于轻量级动态优化的低电压处理器。基于低电压处理器中的瞬态错误在指令级的局部性,提出基于动态优化的软硬件协同设计的低电压处理器设计方法。该方法在软硬件之间,引入一个基于动态转译技术的轻量级的动态优化器。该优化器在程序运行时实时收集程序的瞬态错误信息,在处理器空闲时分析这些错误信息并在热点错误指令之前插入瞬态错误警报。当程序再次执行时,如果优化器发现特定的指令序列不断引起瞬态错误,立即激活预留在该指令序列之前的瞬态错误警报,以通知硬件采取措施,避免该指令未来执行时的瞬态错误。该方法通过软硬件协同设计以极低的成本消除了高达95%以上的瞬态错误,不但大幅减少因为纠错导致的性能损失和功耗损失,而且使得底层的容错硬件可以设计的非常简单和鲁棒,有效提高系统的容错能力和能效。
[Abstract]:With the development of mobile Internet and Internet of Things, embedded processors based on ARM are becoming more and more popular, such as smart phones and smart tablets. On the one hand, the binary compatibility of the code has become a major impediment to the ability of the new processor architecture to access the embedded market. On the other hand, these processors are often powered by batteries and are subject to severe power consumption problems. The dynamic binary translation technology can not only effectively solve the code compatibility problem, realize cross-platform execution, but also can obtain the operation information of the program in real time, and carry out dynamic optimization on the program to obtain the optimal energy efficiency. In this paper, the key technology of dynamic binary translation is studied, and an acceleration method for dynamic translation is proposed, and the binary translation technology and the transient error adaptive low-voltage processor design technology are combined with the cross-platform characteristic and the dynamic optimization characteristic of the binary translation. So as to effectively improve the energy efficiency of the processor. The main content and innovation point of this paper are as follows:1. Dynamic translation method based on the characteristic of transfer instruction. A dynamic translation method of direct mapping and instruction type translation strategy combination is proposed based on the different features of the transfer target address inside and outside the function. the transfer instruction in the function is directly mapped by the branch instruction corresponding to the target structure, and the branch instruction of the high-efficiency translation condition is not required to be generated by the instruction forwarding and decoding before and after the transfer, and the source register is not required to be generated to the memory synchronization instruction; and the function-to-function transfer instruction is executed, The method of dynamic translation based on the load balance of the cache is based on the transfer of the function of the source program and the other transfer instruction. A software and hardware co-translation method based on instruction and data cache access load dynamic balance is proposed for the problem of the decrease of the translator's performance due to the significant increase of the instruction and data cache access load and the unbalanced increase in the dynamic translation. The method comprises the following steps of: designing a cache load balance state for a processor, dividing the data cache into a normal area and a load balance area, and caching normal program data in the normal area; the load balance region absorbs the partial load generated on the instruction cache when the dynamic translator scheduler absorbs the partial load generated on the instruction cache when the source machine code space address is converted to the target machine code space address by the load conversion channel absorption dynamic translator scheduler, A low voltage processor based on a single-cycle error correction of a transient error prediction model. Based on the local and the predictability of the transient error in the low voltage processor in the pipeline, a low-voltage processor design method for the single-cycle error correction of the hardware and software co-design is proposed. The core idea of the method is to set up a processor transient error prediction model based on the dynamic translation technology. The model predicts the possible error of the instruction stream when the program is compiled. For those instruction streams that may be wrong, the programming interface can be eliminated by the processor's transient error, and the possible transient errors can be avoided at the time of the compilation, so that the fault-tolerance and energy efficiency of the system can be effectively improved. Based on the local error of the low voltage processor, the design method of the low voltage processor based on the dynamic optimization of the hardware and software is proposed. The method introduces a lightweight dynamic optimizer based on dynamic translation technology between hardware and software. The optimizer collects the transient error information of the program in real time while the processor is running, analyzes the error messages when the processor is idle and inserts a transient error alert before the hotspot error instruction. When the program is executed again, if the optimizer finds that a particular instruction sequence continues to cause a transient error, the transient error alert that is reserved before the instruction sequence is immediately activated to notify the hardware to take steps to avoid a transient error in the future execution of the instruction. The method eliminates the transient error of up to 95% at a very low cost through the cooperative design of the hardware and software, not only greatly reduces the performance loss and the power loss caused by error correction, but also makes the fault-tolerant hardware of the bottom layer simple and robust in design, And the fault tolerance and energy efficiency of the system can be effectively improved.
【学位授予单位】：浙江大学
【学位级别】：博士
【学位授予年份】：2016
【分类号】：TP332

【相似文献】